Integrated circuits can be found in many of today's consumer electronics such as cell phones, video camera, portable music players, computers, printers, etc. Integrated circuits may comprise a combination of various active and passive semiconductor devices and their interconnections. The formation of these semiconductor devices and interconnections typically include patterning steps where a mask (such as a photoresist mask) is formed over one or more layers on a substrate and exposed portions of the layers underlying the mask selectively removed. In this manner, the desired design and layout for an integrated circuit can be transferred onto a semiconductor wafer.
FIGS. 1A to 1C illustrate a known method for patterning semiconductor devices 100. In FIG. 1A, a first dielectric layer 120, a first metallic layer 140 and a second dielectric layer 160 are deposited over a substrate 101. The first dielectric layer 120 being the lowermost layer in the stack and the second dielectric layer 160 being the uppermost layer in the stack. A photoresist layer is deposited over the second dielectric layer 160 and then developed to form a patterned photoresist mask 180. The second dielectric layer 160 and the first metallic layer 140 are subsequently etched in accordance with the photoresist mask 180 using a plasma etching process.
During the etching of the second dielectric 160 and first metallic layer 140, etch residues 190 are formed along the sidewalls of the photoresist mask 180, second dielectric layer 160 and first metallic layer 140 as shown in FIG. 1B. These sidewall etch residues are a by-product of the plasma etching process and may include hardened photoresist material, etch residue generated as a result of chemical reactions occurring during the plasma etch, sputtered on materials, or re-deposited materials or combinations thereof. In this example, the sidewall etch residues 190 are conductive since the first layer is made of metallic material 140.
FIG. 1C shows the semiconductor structure 100 of FIG. 1B after etching has completed and the photoresist mask 180 is removed by a plasma based photoresist strip process. The plasma based photoresist strip process is typically followed by a wet etch process to remove the sidewall etch residue 190. Commercially available chemical strippers such as CR solution (which comprises sulphuric acid and hydrogen peroxide), HF or NE 111 (from Air Products) may be used in the wet etch process. Depending on factors such as the materials being etched and/or process conditions for the plasma dry etch, the sidewall etch residues 190 may still remain after the wet etch process for instance as illustrated in FIG. 1C. The residual sidewall etch residues 190 are undesirable and can result in problems such as device failure, current leakage and degradation of device reliability.
FIG. 2 shows a conventional metal-insulator-metal (MIM) capacitor 200. MIM capacitors are semiconductor devices formed by sandwiching one or more layers of dielectric material between a top and a bottom conductive electrode. The electrodes often include metal layers or alloys thereof. The metal layers or alloys can comprise some or all of top and/or bottom electrodes of the capacitor. In FIG. 2, the MIM capacitor 200 is formed on a dielectric layer 210 over a substrate 201 and comprises metallic bottom and top electrodes (220, 240) separated by a capacitor dielectric layer 230. The top electrode 240 is smaller than the bottom electrode 220, creating an area for via contacts 250 to the bottom electrode 220. Via contacts 260 are also provided for electrical connection to the top electrode 240.
The MIM capacitor of FIG. 2 is formed by patterning the top and bottom electrodes (220, 240) using the method described in relation to FIGS. 1A to 1C. During the etching of the bottom and top electrodes, conductive etch residues 280 are formed along the sidewalls of the capacitor. In this illustrated example, wet clean processes carried out post top and bottom electrode plasma etch are not able to remove the sidewall etch residues 280 effectively. Consequently, the sidewall etch residues 280 protrude above the level of bottom and top electrodes (220, 240) shorting with an adjacent via contact (250, 260). Since the polymer fences 280 are conductive, such a phenomena is undesirable as it results in problems such as current leakage and degradation of device reliability. A possible solution is to use a more aggressive chemical stripper to improve etch residue removal but this has the problem of damaging the capacitor dielectric 230 which in turn leads to degradation of capacitor performance.
In view of the foregoing discussion, it is desirable to provide a method for reducing the extent of etch residue remaining post etch while minimizing damage to the semiconductor device.